Q1 (3 points) : For this problem, we will use the following loop:
for (k=n; k>=0; k) x[k] = y[k+1] – 2.0 * y[k];
If we assume:
The above code could be written as the following MIPS assembly code:
Loop: LD 
F2, 
8(R1) 

LD 
F4, 
0(R1) 

MULTD 
F6, 
F4, F0 

SUBD 
F8, 
F2, F6 

SD 
F8, 
0(R2) 

SUBI 
R1, 
R1, #8 
#same as DADDUI R1, R1, #8 
SUBI 
R2, 
R2, #8 

BNEZ 
R2, 
Loop 
Using the following table for instruction latencies
Instruction/Operation Type 
Latency in Clock Cycles 
Double Load 
1 
Double Store 
0 
FP Multiply 
5 
Cycle Instruction/stall
Cycle Instruction/stall
Cycle Instruction/stall
Q2 : (7 points) Show scheduling of the following code: L.D F2, 0(R2)
L.D F4, 100(R3)
ADD.D F8, F2, F2
MUL.D F6, F4, F8
SUB.D F6, F2, F4
takes 25 cycles.
LOAD units, two FP multipliers and three FP adders. Load unit takes one execution cycle for address calculation and a second one for memory access, FP
multipliers take 7 cycles and FP adders take 4 cycles.
(how are the sources of slowdown in one
structure avoided by the “better” structure).
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