COSE222 Computer Architecture
Final Project
Add new instructions to the provided single-cycle CPU, so that the 2 programs in the zip file can be executed on the new CPU. The programs will display 5 and A alternatively on HEX0 of the DE0 board with some interval of time if the CPU is implemented correctly.
http://esca.korea.ac.kr/teaching/cose222_CA/milestones/final-project_milestone3.zip
Design Requirement:
You are free to change anything in the given CPU except the register file o The provided register file has 2 read ports and 1 write port.
You should probably follow the steps below;
- Compile the programs under Eclipse environment and generate the MIPS code
- Open dump to see what kinds of MIPS instructions you should implement
ü Figure out which instructions are already there in the provided CPU and what are not there
- Implement those new instructions to the provided single-cycle CPU
- Simulate with ModelSim to debug and validate your design 5. Synthesize the single-cycle CPU with the mif file
- Download the bitstream to the DE0 board.
What and How to submit:
- Create a (up to) 2-min video clip (with your smartphone or any other convenient means), showing o Your smiling face to camera
- 7 segment output on DE0 board
AND verbally explaining the followings:
- What instructions you added to the CPU, and how you figured out those instructions to be added to the CPU
- CPU design change (please elaborate this!) o ModelSim simulation output
- Upload both the video clip and zipped Verilog source to Blackboard
Note: This is an individual project. You are welcome to discuss, but DO NOT COPY solutions. If you are found to copy solutions from others or slightly modify the solutions from others, both of you will be given 0 credits.
