Flip Flop Sample Assignment
I. D-Flip Flop
A. List of Components and Equipment and DataSheet
1. AND Gate
2. XOR Gate
3. Probe
4. Vcc
5. Ground
6. Clock Pulse
7. D-Flip Flop
8. 7 Segment Display
9. IC 7447N
![Flip Flop Image 1 Flip Flop Image 1](https://www.assignmenthelp.net/webimg/yah/images/flip-flop-image-1.jpg)
Figure II‑1: IC 7447 Connection Diagram
![Flip Flop Image 2 Flip Flop Image 2](https://www.assignmenthelp.net/webimg/yah/images/flip-flop-image-2.jpg)
Figure II‑2 Electrical Characteristics
![Flip Flop Image 3 Flip Flop Image 3](https://www.assignmenthelp.net/webimg/yah/images/flip-flop-image-3.jpg)
Figure II‑3 Internal Circuit
B. Design
S1 > S3 > S6 > S0
Excitation Table for D Flip Flop
Qn |
Qn+1 |
Dn |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
0 |
0 |
1 |
1 |
1 |
State Table
Present State |
Next State | ||||||||
Q2 |
Q1 |
Q0 |
Q2 |
Q1 |
Q0 |
D2 |
D1 |
D0 | |
S1 |
0 |
0 |
1 |
0 |
1 |
1 |
0 |
1 |
1 |
S3 |
0 |
1 |
1 |
1 |
1 |
0 |
1 |
1 |
0 |
S6 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
S0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
1 |
K- Map
D2
Q0\Q2Q1 |
00 |
01 |
11 |
10 |
0 |
0 |
X |
0 |
X |
1 |
0 |
1 |
X |
X |
D2= Q2’Q1
D1
Q0\Q2Q1 |
00 |
01 |
11 |
10 |
0 |
0 |
X |
0 |
X |
1 |
1 |
1 |
X |
X |
D1 = Q0
D0
Q0\Q2Q1 |
00 |
01 |
11 |
10 |
0 |
1 |
X |
0 |
X |
1 |
1 |
0 |
X |
X |
D0 = Q1’
![Flip Flop Image 4 Flip Flop Image 4](https://www.assignmenthelp.net/webimg/yah/images/flip-flop-image-4.jpg)
Figure II‑4 Circuit Diagram
C. Results:
The given circuit generates a series as specified with each clock pulse.
![Flip Flop Image 5 Flip Flop Image 5](https://www.assignmenthelp.net/webimg/yah/images/flip-flop-image-5.jpg)
Figure II‑5 Output 1
![Flip Flop Image 6 Flip Flop Image 6](https://www.assignmenthelp.net/webimg/yah/images/flip-flop-image-6.jpg)
Figure II‑6 Output 2
![Flip Flop Image 7 Flip Flop Image 7](https://www.assignmenthelp.net/webimg/yah/images/flip-flop-image-7.jpg)
Figure II‑7 Output 3
![Flip Flop Image 8 Flip Flop Image 8](https://www.assignmenthelp.net/webimg/yah/images/flip-flop-image-8.jpg)
Figure II‑8 Output 4
D. Constraints:
The speed with which the numbers refresh depends on clock pulse frequency and can be modified only by changing the clock pulse frequency.
E. Discussion and Conclusion:
Synchronous counters run on triggering by clock pulse. Manual intervention or externa input is not required.
The next value coming out of the flip-flop is achieved by changing D value of the flip-flop.
The output matches with the theoretical calculations.
II. JK-Flip Flop
A. List of Components and Equipment and DataSheet
1. AND Gate
2. OR Gate
3. Probe
4. Vcc
5. Ground
6. Clock Pulse
7. JK-Flip Flop
8. 7 Segment Display
9. IC 7447N
![Flip Flop Image 9 Flip Flop Image 9](https://www.assignmenthelp.net/webimg/yah/images/flip-flop-image-9.jpg)
Figure III‑1 IC7447 Connection Diagram
![Flip Flop Image 10 Flip Flop Image 10](https://www.assignmenthelp.net/webimg/yah/images/flip-flop-image-10.jpg)
Figure III‑2 Electrical Characteristics
![Flip Flop Image 11 Flip Flop Image 11](https://www.assignmenthelp.net/webimg/yah/images/flip-flop-image-11.jpg)
Figure III‑3 Logic Diagram
B. Design
S1 > S3 > S8 > S6 > S13 > S10 > S0
Excitation Table for J-K Flip Flop
Qn |
Qn+1 |
Jn |
Kn |
0 |
0 |
0 |
X |
0 |
1 |
1 |
X |
1 |
0 |
X |
1 |
1 |
1 |
X |
0 |
State Table
Present State |
Next State | |||||||||||||||
Q3 |
Q2 |
Q1 |
Q0 |
Q3 |
Q2 |
Q1 |
Q0 |
J3 |
K3 |
J2 |
K2 |
J1 |
K1 |
J0 |
K0 | |
S1 |
0 |
0 |
0 |
1 |
0 |
0 |
1 |
1 |
0 |
X |
0 |
X |
1 |
X |
X |
0 |
S3 |
0 |
0 |
1 |
1 |
1 |
0 |
0 |
0 |
1 |
X |
0 |
X |
X |
1 |
X |
1 |
S8 |
1 |
0 |
0 |
0 |
0 |
1 |
1 |
0 |
X |
1 |
1 |
X |
1 |
X |
0 |
X |
S6 |
0 |
1 |
1 |
0 |
1 |
1 |
0 |
1 |
1 |
X |
X |
0 |
X |
1 |
1 |
X |
S13 |
1 |
1 |
0 |
1 |
1 |
0 |
1 |
0 |
X |
0 |
X |
1 |
1 |
X |
X |
1 |
S10 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
X |
1 |
0 |
X |
X |
1 |
0 |
X |
S0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
X |
0 |
X |
0 |
X |
1 |
X |
K-Map
J3
Q3Q2\Q1Q0 |
00 |
01 |
11 |
10 |
00 |
0 |
0 |
1 |
X |
01 |
X |
X |
X |
1 |
11 |
X |
X |
X |
X |
10 |
X |
X |
X |
X |
J3 = Q1
K3
Q3Q2\Q1Q0 |
00 |
01 |
11 |
10 |
00 |
X |
X |
X |
X |
01 |
X |
X |
X |
X |
11 |
X |
0 |
X |
X |
10 |
1 |
X |
X |
1 |
K3 = Q2’
J2
Q3Q2\Q1Q0 |
00 |
01 |
11 |
10 |
00 |
0 |
0 |
0 |
X |
01 |
X |
X |
X |
X |
11 |
X |
X |
X |
X |
10 |
1 |
X |
X |
0 |
J2= Q3Q1’
K2
Q3Q2\Q1Q0 |
00 |
01 |
11 |
10 |
00 |
X |
X |
X |
X |
01 |
X |
X |
X |
0 |
11 |
X |
1 |
X |
X |
10 |
X |
X |
X |
X |
K2 = Q1’
J1
Q3Q2\Q1Q0 |
00 |
01 |
11 |
10 |
00 |
0 |
1 |
X |
X |
01 |
X |
X |
X |
X |
11 |
X |
1 |
X |
X |
10 |
1 |
X |
X |
X |
J1 = Q0+Q3
K1
Q3Q2\Q1Q0 |
00 |
01 |
11 |
10 |
00 |
X |
X |
1 |
X |
01 |
X |
X |
X |
1 |
11 |
X |
X |
X |
X |
10 |
X |
X |
X |
1 |
K1= 1
J0
Q3Q2\Q1Q0 |
00 |
01 |
11 |
10 |
00 |
1 |
X |
X |
X |
01 |
X |
X |
X |
1 |
11 |
X |
X |
X |
X |
10 |
0 |
X |
X |
0 |
J0 = Q3’
K0
Q3Q2\Q1Q0 |
00 |
01 |
11 |
10 |
00 |
X |
0 |
1 |
X |
01 |
X |
X |
X |
X |
11 |
X |
1 |
X |
X |
10 |
X |
X |
X |
X |
J0= Q2+Q1
![Flip Flop Image 12 Flip Flop Image 12](https://www.assignmenthelp.net/webimg/yah/images/flip-flop-image-12.jpg)
Figure III‑4 Circuit Diagram
C. Result
![Flip Flop Image 13 Flip Flop Image 13](https://www.assignmenthelp.net/webimg/yah/images/flip-flop-image-13.jpg)
Figure III‑5 Output 1
Figure III‑6 Output 2
![Flip Flop Image 15 Flip Flop Image 15](https://www.assignmenthelp.net/webimg/yah/images/flip-flop-image-15.jpg)
Figure III‑7 Output 3
![Flip Flop Image 16 Flip Flop Image 16](https://www.assignmenthelp.net/webimg/yah/images/flip-flop-image-16.jpg)
Figure III‑8 Output 4
![Flip Flop Image 17 Flip Flop Image 17](https://www.assignmenthelp.net/webimg/yah/images/flip-flop-image-17.jpg)
Figure III‑9 Output 5
![Flip Flop Image 18 Flip Flop Image 18](https://www.assignmenthelp.net/webimg/yah/images/flip-flop-image-18.jpg)
Figure III‑10 Output 6
![Flip Flop Image 19 Flip Flop Image 19](https://www.assignmenthelp.net/webimg/yah/images/flip-flop-image-19.jpg)
Figure III‑11 Output 7
![Flip Flop Image 20 Flip Flop Image 20](https://www.assignmenthelp.net/webimg/yah/images/flip-flop-image-20.jpg)
Figure III‑12 Output 8
D. Constraints:
The speed with which the numbers refresh depends on clock pulse frequency and can be modified only by changing the clock pulse frequency.
For some cases some unwanted text appears because the IC 7447 is not made for values above 9.
E. Discussion and Conclusion:
Synchronous counters run on triggering by clock pulse. Manual intervention or externa input is not required.
The next value coming out of the flip-flop is achieved by changing J and K value of the flip-flop.
The output matches with the theoretical calculations when the numbers range 0-9. But since IC7447 is meant only for BCD values, for two-digit values it does not show correct value. However, we can see that the flip flops work correct and the output is seen in LEDs.
III. References
Dflipflop . (n.d.). Retrieved from hyperphysics: http://hyperphysics.phy-astr.gsu.edu/hbase/Electronic/Dflipflop.html
d-flip-flops . (n.d.). Retrieved from circuitdigest: https://circuitdigest.com/electronic-circuits/d-flip-flops
jkflipflop . (n.d.). Retrieved from hyperphysics: http://hyperphysics.phy-astr.gsu.edu/hbase/Electronic/jkflipflop.html
sequential . (n.d.). Retrieved from electronics: https://www.electronics-tutorials.ws/sequential/seq_2.html