Where the clock frequency the processor mhz

I. (20 pts) Multiple Choice

1. The von Neumann architecture is based on which concept? _______

2. The processing required for a single instruction is called a(n) __________ cycle.

A. execute B. fetch

4. A __________ is the high-level set of rules for exchanging packets of data between devices.

A. bus B. protocol

6. Individual blocks or records have a unique address based on physical location with __________.

A. associative B. physical access

8. ________ is the simplest mapping technique and maps each block of main memory into only one possible cache line.

A. Direct mapping B. Associative mapping

10. In reference to access time to a two-level memory, a _________ occurs if an accessed word is not found in the faster memory.

A. miss B. hit

Address of instruction sets that is being executed currently.

What does the Instruction Register (IR) holds?

3. Briefly describe the Instruction Cycle State with Interrupts listed below.

Instruction fetch (IF): PC is pointing to the next instruction sets that is going to be executed

Operand store (OS) or Write Back (WB): Data are stored and write in register or memory if it required.

Interrupt (IT): It halts the execution in response to signal from hardware at random time.

Random: memory which can be accessed randomly to any location.

Associated: Memory unit whose stored data can be access by content of the data no address.

3) Consider the following code:

for (i=0; i<20; i++)

2. Give one example of the temporal locality in the code.

j refers to a[i] and i refer to a[i] temporal

L3: Small memory size where data is stored and lost when computer is power off.

2) What is the main advantage of the LRU replacement algorithms in the cache design?

Advantage:

1. Simplest technique

What are the main advantage and disadvantage of cache memory write back policy?

Advantage:

4. What is the difference between the Unified Cache and Split Caches?

Unified caches have high rate of hit and only one cache is implemented where as in split it has more than one and it allow parallel execution.

CPI = 1*70% + 4*10% + 8*20% = 2.7

MIPS rate = f/(CPI x 10^6), where f is the clock frequency of the processor.