Using bit adder and arithmetic logic extender block

Class Exercise 3 – ALU

Design an ALU with two 8-bit inputs A and B, and control inputs x, y, and z. The ALU should support the operations described in the Table.

c. Write the VHDL code
i. Implement a slice of the AL-Extender in VHDL
ii. Implement the ALU in VHDL using the AL-Extender of from part i as a component. Be sure to include the AL-Extender functions for the adder carry in.

iii. Implement the ALU by writing the code for the AL-Extender using 8- bit operations (i.e. don’t use the AL-Extender slice component).

entity ALU_HW3_3 is
Port ( a : in STD_LOGIC_VECTOR (7 downto 0);
b : in STD_LOGIC_VECTOR (7 downto 0);
x : in STD_LOGIC;
y : in STD_LOGIC;
z : in STD_LOGIC;
s : out STD_LOGIC_VECTOR (7 downto 0));
end ALU_HW3_3;

architecture Behavioral of ALU_HW3_3 is

when "001" => -- s = a + b
ia <= a;
ib <= b;
ci <= '0';

when "010" => -- s = a * 2
ia <= std_logic_vector(unsigned(a) sll 1); -- or ia <= a(6 downto 0) & '0';
ib <= (others => '0');
ci <= '0';

when "111" => -- s = NOT a
ia <= NOT a;
ib <= (others => '0');
ci <= '0';

when others =>
ia <= (others => 'X');
ib <= (others => 'X');
ci <= 'X';
end case;
end process;