The pmos transistor displays reverse behavior
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Section 5.4 | 191 |
Gate-Drain Capacitance Cgd12
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∆V | Cgd1 | Vout | Vout | ||||||
Vin | M1 | ∆V | ∆V |
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192 | Ceq | = |
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THE CMOS INVERTER | Chapter 5 | ||
(5.13) |
with Cj0 the junction capacitance per unit area under zero-bias conditions. An expression for Keq was derived in Eq. (3.11) and is repeated here for convenience
Keq | = | [ | ( | φ0 | –Vhigh | )1 | –m | – | ( | φ0 | –Vlow | )1 | –m |
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with φ0 the built-in junction potential and m the grading coefficient of the junction. Observe that the junction voltage is defined to be negative for reverse-biased junctions.
Example 5.3 | |||
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Bottom plate: Keq (m = 0.5, φ0 = 0.9) = 0.57, | |||
Sidewall: Keqsw (m = 0.44, φ0 = 0.9) = 0.61 |
During the low-to-high transition, Vlow and Vhighequal 0 V and −1.25 V, respectively, resulting in higher values for Keq,
Bottom plate: Keq (m = 0.5, φ0 = 0.9) = 0.79,
Sidewall: Keqsw (m = 0.44, φ0 = 0.9) = 0.81
Using this approach, the junction capacitance can be replaced by a linear component and treated as any other device capacitance. The result of the linearization is a minor dis-tortion of the voltage waveforms. The logic delays are not significantly influenced by this simplification.