Logic block finishes before the clock period

	chapter10_141.fm Page 64 Tuesday, April 16, 2002 9:12 AM
	Section 10.3		64

7. Variation in chip temperature across the die causes variations in clock buffer delay. The use of feedback circuits based on delay locked loops as discussed later in this chapter can easily compensate for temperature variations.

8. Power supply variation is a significant component of jitter as it impacts the cycle to cycle delay through clock buffers. High frequency power supply variation can be reduced by addition of on-chip decoupling capacitors. Unfortunately, decoupling capacitors require a significant amount of area and efficient packaging solutions must be leveraged to reduce chip area.

	10.3.4


	binational logic is separated by transparent latches. In an edge-triggered system, the worst




	steal time from following stages. This flexibility, allows an overall performance increase.
	Note that the latch based methodology is nothing more than adding logic between latches




	the combinational logic block A (CLB_A) on the falling edge of CLK1 (at edge 2) and it
	has a maximum time equal to the TCLK/2 to evaluate (that is, the entire low phase of CLK1). On the falling edge of CLK2 (at edge 3), the output CLB_A is latched and the




	available to perform the combination of CLB_A and CLB_B is TCLK.

					L2		TIMING ISSUES IN DIGITAL CIRCUITS
65							TIMING ISSUES IN DIGITAL CIRCUITS
65							B	CLB_B	L1	Q	C
In	L1	Q	A	CLB_A tpd,A					L1
	D				D	Q			D				D
	D				D	Q		tpd,B				tpd,C	D
CLK1					CLK2			tpd,B				tpd,C
CLK1					CLK2		CLK1

TCLK

CLK1	1	2	compute CLB_A
CLK1		launch A	compute CLB_A
CLK2		launch A			compute CLB_B

Figure 10.26 Latch-based design in which transparent latches are separated by combinational logic.




borrowing [Bernstein00]. This approach requires no explicit design changes, as the pass-
ing of slack from one block to the next is automatic. The key advantage of slack borrow-




stages. This implies that the clock rate can be higher than the worst case critical path!
Slack passing happens due to the level sensitive nature of latches. In Figure 10.26,




CLB_A is valid. This implies that the maximum time available for CLB_A is its phase time
(i.e., the low phase of CLK1) and any left over time from the previous computation. For-


L1		L2	L1
D	Q	D		CLB_A	CLB_B	D	Q		D	Q	CLB_C
CLK1		CLK2	CLK1					CLK2