Logic block finishes before the clock period
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Section 10.3 | 64 |
7. Variation in chip temperature across the die causes variations in clock buffer delay. The use of feedback circuits based on delay locked loops as discussed later in this chapter can easily compensate for temperature variations.
8. Power supply variation is a significant component of jitter as it impacts the cycle to cycle delay through clock buffers. High frequency power supply variation can be reduced by addition of on-chip decoupling capacitors. Unfortunately, decoupling capacitors require a significant amount of area and efficient packaging solutions must be leveraged to reduce chip area.
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Figure 10.26 Latch-based design in which transparent latches are separated by combinational logic.
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CLK1 | CLK2 | CLK1 |
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