Fetch the sample from the input signals circular buffer

y(4) = h(0) x(4) + h(1) x(3) + h(2) x(2) + h(3) x(1)

y(5) = h(0) x(5) + h(1) x(4) + h(2) x(3) + h(3) x(2)

In the example shown in Figure 17.88 , the coeffi cients are stored in a reverse manner.

A simple summary fl owchart for these operations is shown in Figure 17.89 . For Analog Devices DSPs , all operations within the fi lter loop are completed in one instruction cycle , thereby greatly increasing effi ciency. This is referred to as zero-overhead looping . The actual FIR fi lter assembly code for the ADSP-21xx family of fi xed-point DSPs is shown in Figure 17.90 . The arrows in the diagram point to the actual executable instructions, and the rest of the code are simply comments added for clarifi cation.

4. Zero the accumulator

5. Implement filter (control the loop through each of the coefficients)

Figure 17.89 : Pseudocode for FIR fi lter program using a DSP with circular buffering

.MODULE fir_sub;
{ FIR Filter Subroutine
Calling Parameters
I0 --> Oldest input data value in delay line I4 --> Beginning of filter coefficient table L0 = Filter length (N)
L4 = Filter length (N)
M1,M5 = 1
CNTR = Filter length - 1 (N-1)
Return Values
MR1 = Sum of products (rounded and saturated) I0 --> Oldest input data value in delay line I4 --> Beginning of filter coefficient table Altered Registers
MX0,MY0,MR
Computation Time
(N - 1) + 6 cycles = N + 5 cycles
All coefficients are assumed to be in 1.15 format. }

.ENDMOD;