CPU & Control Processing
what is control processing unit ?
Traditionally, the term "CPU" refers to the Central Processing Unit, which is the primary component of a computer responsible for executing instructions of a computer program. The CPU performs arithmetic and logic operations, manages data movement within the computer, and controls other hardware components to execute the instructions of a program.
Question 1:
(a) Explain how CPU architectures may differ between brands of computer systems, using diagrams.
(b) Explain the statement about the Arithmetic and Logic Unit (ALU) using diagrams.
(c) Describe and provide diagrams for five components of the Control Unit.
Clock Generator: Provides timing signals to synchronize components.
Instruction Register (IR): Holds the current instruction.
Question 2:
(a) Use a hand sketch diagram to explain the instruction cycle phases.
Decode Instruction: Fetched instruction is decoded for its operation.
Fetch Operand: CPU retrieves data from memory if required.
(b) Explain the terms A, R, PC, and EA in addressing modes.
Effective Address (EA): The actual memory address used in an instruction.
(c) Differentiate between Reduced Instruction Set Computing (RISC) and Complex Instruction Set Computers (CISC) architectures.
RISC and CISC architectures differ in their design philosophy:
| spect | Reduced Instruction Set Computing (RISC) | Complex Instruction Set Computers (CISC) |
|---|---|---|
| Philosophy | Emphasizes simple and efficient instructions. | Offers a wide range of complex and versatile instructions. |
| Instruction Types | Limited number of instruction types. | Wide variety of instruction types. |
| Addressing Modes | Few addressing modes. | Many addressing modes for flexibility. |
| Operand Access | Most operations involve registers. | Can involve memory directly in operations. |
| Execution Time | Instructions have uniform execution time. | Instructions may have varying execution times. |
| Pipeline Efficiency | Pipeline-friendly design for frequent execution. | Pipeline may be complex due to diverse instructions. |
| Memory Load/Store | Often uses separate load and store instructions. | May allow memory operations directly with other instructions. |
| Code Size | RISC instructions are generally shorter. | CISC instructions can be longer due to complexity. |
| Hardware Complexity | Simpler hardware design. | More complex hardware to handle diverse instructions. |
| Focus on Compiler | Rely more on optimizing compilers. | Instructions designed to work efficiently without extensive compiler optimization. |
Question 3:
(a) Explain the purpose of further utilizing parallel processing for simultaneous data processing tasks.
(b) Provide explanations for the underachieving parallel processing concepts.
Parallelism and Pipelining: Overlapping instruction stages to increase throughput.
Overlapped CPU and I/O: Concurrently handling computation and input/output.
(c) Explain the three architectural configurations of parallel computers.
Array Processors: Multiple processors work on different elements of data arrays.
Multiprocessor Systems: Multiple processors execute instructions independently.
Question 4:
(a) Discuss Flynn's classification in relation to pipelining.
MIMD: Multiple processors executing independent instructions.
(b) Explain the role of the instruction set in computer architecture evolution.
The instruction set determines how machine language programs are constructed. Evolution in architecture aims to maximize speed, minimize execution time, development cost, and sale price. This involves optimizing instruction sets for common tasks and enhancing hardware efficiency.
