Assist spectrum designs none physical bit stream blind

Node-to-Network Interface in Scalable Multiprocessors

CS 258, Spring 99

• Input buffer overflow
– N-1 queue over-commitment => must slow sources – reserve space per source (credit)
» when available for reuse?

• Ack or Higher level
– Refuse input when full
» backpressure in reliable network
» tree saturation
» deadlock free
» what happens to traffic not bound for congested dest?

	CS258 S99	2

» Each may generate a response, which cannot be sent!» What happens when internal buffering is full?

• logically independent request/reply networks – physical networks
– virtual channels with separate input/output queues

	CS258 S99	3

Scalable Network

Message

		° ° °


		Communication Assist
				– translation
				– translation
		P	Node Architecture


– scheduling	M

• Key Design Issue:
• How much interpretation of the message?

	CS258 S99	4


– blind, physical DMA		nCUBE, iPSC, . . .
• User/System
		*CM-5, T**
		J-Machine,

– Processing, translation		Paragon, Meiko
CS-2 • Global physical address
		RP3, BBN, T3D

	CS258 S99

Data	Dest

DMA
channels

Addr		Addr
Length		Length
Length	interrupt	Length
Rdy		Rdy
Memory

• DMA controlled by regs, generates interrupts

• Physical => OS initiates transfers

	dest addr

• Receive

– must receive into system buffer, since no interpretation inCA

	CS258 S99	6

	

Switch

Addr	Addr	Addr		Addr
				Addr
				Length	Length	Length

Memory

Memory

3/10/99

CS258 S99

Host Memory	NIC

Data	Addr Len		TX
Data	Addr Len		RX	len
	Status
	Next
	Addr Len	Addr Len
	Status	Status	Proc
	Next
	Addr Len	Addr Len
	Status	Status
	Next	Next
	Next

Data	Dest



Mem	P		Mem
Mem	P		Mem

3/10/99	CS258 S99	9

User Level Network ports Virtual address space

port	Processor

Registers

Program counter

	CS258 S99	10

Processing	Diagnostics network
	Control network


	PM PM
	Processing	Control
partition	partition	processors

• tag per message

	$		Data
		$	networks
• context switching?			networks
			NI
	ctrl	SRAM	NI

	DRAM	Vector	DRAM	DRAM	Vector
	DRAM	unit	DRAM	DRAM	unit
	ctrl		ctrl	ctrl
chip	DRAM		DRAM	DRAM

D ata	Ad dress

M e m		M em	P

• Hardware support to vector to address specified in message
– message ports in registers

	CS258 S99	12

• HW support to queue msgs and dispatch to msg handler task
	CS258 S99

3/10/99	CS258 S99	14

*T: Network Co-Processor

	CS258 S99	15

Interface unit

• Nodes integrate
communication with
computation on
systolic basis

	CS258 S99	16

Dedicated processing without dedicated hardware design

3/10/99	CS258 S99	17

Mem	M P		Mem	M P	NI
P	M P		P	M P	NI

User	System	User

	CS258 S99	18

Levels of Network Transaction

Network

Mem	M P		° ° °	NI	M P
P	M P		° ° °	NI	M P	P

• User Processor stores cmd / msg / data into shared output queue – must still check for output queue full (or make elastic)
• Communication assists make transaction happen
– checking, translation, scheduling, transport, interpretation
• Effect observed on destination address space and/or events• Protocol divided between two layers

3/10/99	CS258 S99	19

16	175 MB/s Duplex	rte

i860xp	Mem	$	2048 B	° ° °
	Mem		2048 B	° ° °
			NI
50 MHz			NI
50 MHz			sDMA
16 KB $			sDMA
4-way			rDMA
32B Block	P	M P	rDMA

	CS258 S99	20