Arm and thumb- instruction set quick reference cardkey tablesrm

ARM® and Thumb®-2 Instruction Set
Quick Reference Card

<prefix> See Table Prefixes for Parallel instructions
{IA|IB|DA|DB} Increment After, Increment Before, Decrement After, or Decrement Before.

IB and DA are not available in Thumb state. If omitted, defaults to IA.

+ or –. (+ may be omitted.)
See Table ARM architecture versions.

Interrupt flags. One or more of a, i, f (abort, interrupt, fast interrupt).

User mode privilege if T present.

Rounds result to nearest if R present, otherwise truncates result.

Operation		§			Notes
		T2 T2 T2 T2	BFC Rd, #<lsb>, #<width> BFI Rd, Rn, #<lsb>, #<width> SBFX Rd, Rn, #<lsb>, #<width> UBFX Rd, Rn, #<lsb>, #<width>
			PKHBT Rd, Rn, Rm{, LSL #<sh>} PKHTB Rd, Rn, Rm{, ASR #<sh>}	Rd[15:0] := Rn[15:0], Rd[31:16] := (Rm LSL sh)[31:16]. sh 0-31. Rd[31:16] := Rn[31:16], Rd[15:0] := (Rm ASR sh)[15:0]. sh 1-32.
Signed extend			SXTH Rd, Rm{, ROR #<sh>} SXTB16 Rd, Rm{, ROR #<sh>} SXTB Rd, Rm{, ROR #<sh>}
Unsigned extend	Halfword to word Two bytes to halfwords		UXTB Rd, Rm{, ROR #<sh>}	Rd[31:0] := ZeroExtend((Rm ROR (8 * sh))[15:0]). sh 0-3.
	Halfword to word, add Two bytes to halfwords, add Byte to word, add			Rd[31:0] := Rn[31:0] + SignExtend((Rm ROR (8 * sh))[15:0]). sh 0-3. Rd[31:16] := Rn[31:16] + SignExtend((Rm ROR (8 * sh))[23:16]), Rd[15:0] := Rn[15:0] + SignExtend((Rm ROR (8 * sh))[7:0]). sh 0-3. Rd[31:0] := Rn[31:0] + SignExtend((Rm ROR (8 * sh))[7:0]). sh 0-3.
		6	UXTAH Rd, Rn, Rm{, ROR #<sh>} UXTAB16 Rd, Rn, Rm{, ROR #<sh>}
	Bits in word Bytes in word Bytes in both halfwords Bytes in low halfword, sign extend	T2 6 6 6	RBIT Rd, Rm REV Rd, Rm REV16 Rd, Rm REVSH Rd, Rm
		6	SEL Rd, Rn, Rm	Rd[7:0] := Rn[7:0] if GE[0] = 1, else Rd[7:0] := Rm[7:0] Bits[15:8], [23:16], [31:24] selected similarly by GE[1], GE[2], GE[3]
		T2		The first instruction after IT has condition cond. The following instructions have condition cond if the corresponding letter is T, or the inverse of cond if the corresponding letter is E. See Table Condition Field for available condition codes.	T U
		5 5J T2 T2 T2	B <label> BL <label> BX Rm BLX <label>	label is this instruction ±32MB (T2: ±16MB). LR := address of next instruction, PC := Rm[31:1]. Change to Thumb if Rm[0] is 1, to ARM if Rm[0] is 0.	N C
Move to or from PSR	PSR to register register to PSR immediate to PSR
	Change processor mode Set endianness				U, N U, N U U, N

ARM Instruction Set
Quick Reference Card

		§ (PLD)				Action if <op> is PLI	Notes
					Preload [address, 32] (data) Preload [address, 32] (data) Preload [label, 32] (data)	Preload [address, 32] (instruction) Preload [address, 32] (instruction) Preload [label, 32] (instruction)


	ARM Word, B, D	ARM SB, H, SH
	offset: – 4095 to +4095 offset: – 4095 to +4095 Full range of {, <opsh>} Full range of {, <opsh>} label within +/– 4092 of current instruction offset: –255 to +255 {, <opsh>} not allowed label within +/– 252 of current instruction Rd1 even, and not r14, Rd2 == Rd1 + 1.	offset: –255 to +255 offset: –255 to +255 {, <opsh>} not allowed {, <opsh>} not allowed Not available - - - -

ARM Instruction Set
Quick Reference Card

	§			Notes
Swap word Swap byte			temp := [Rn], [Rn] := Rm, Rd := temp. temp := ZeroExtend([Rn][7:0]), [Rn][7:0] := Rm[7:0], Rd := temp
			[SPm] := LR, [SPm + 4] := CPSR PC := [Rn], CPSR := [Rn + 4] Prefetch abort or enter debug state. 16-bit bitfield encoded in instruction. Secure Monitor Call exception. 16-bit bitfield encoded in instruction. Formerly SMI.
	6	NOP	None, might not even consume any time.	N
Hints	7 7 7 7 T2 T2 T2 T2		Ensure the completion of memory accesses, Flush processor pipeline and branch prediction logic. Signal event in multiprocessor system. NOP if not implemented.


		Same as Rm, LSL #0 Allowed shifts 0-31 Allowed shifts 1-32 Allowed shifts 1-32 Allowed shifts 1-31

Condition Field

	Equal Not equal Carry Set / Unsigned higher or same Carry Clear / Unsigned lower Negative Positive or zero Overflow No overflow Unsigned higher Unsigned lower or same Signed greater than or equal Signed less than Signed greater than Signed less than or equal Always (normally omitted)	Equal Not equal, or unordered Greater than or equal, or unordered Less than Less than Greater than or equal, or unordered Unordered (at least one NaN operand) Not unordered Greater than, or unordered Less than or equal Greater than or equal Less than, or unordered Greater than Less than or equal, or unordered Always (normally omitted)

	Document Number			Issue B D F H J L

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