The J-K Flip Flop Assignment Help


1. to investigate the operation of J-K flip-flops

2. to appreciate the need for switch debouncing

3. to build and analyse the operation of an asynchronous counter

4. to modify the counter so that it will both count up and count down

5. to design and simulate a three digit decade counter.

Experimental Work

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The truth table of

1. Construct the following circuit on the Logic Tutor, monitoring the clock, Q and QBAR outputs with the on-board LEDs.

2. Complete Table 1, entering an X for ‘don’t care states’.

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Text Box: Note: The clock circuit inside the box is not required when using the Logic Tutor as the switches are already debounced.

Text Box: • what is significant about the output state when Preset = Clear = Logic ‘0’?
• at what part of the clock pulse is the input data inputted into the device?
• at what part of the clock pulse is the output data transferred to the output?
• what clock triggering action does the SN7476 have?

3. Your observations should enable you to answer the following questions:

Simulation- Frequency division properties of J-K Flip-Flops

1. Replace the existing clock circuit with the TTL output of the signal generator.

2. Set the generator to 1 kHz. and Preset = Clear = J = K= ’1’

4. Connect the oscilloscope to both the clock input and Q output and sketch the two observed waveforms above each other on the same time axis.

5. What is the ratio of the output to the input frequency?

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