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A register is used to store multiple bits of data. It can be made by connecting multiple flip flops to each other. The arrangement is such that if we have ‘n’ flip-flops, we can store ‘n’ bits of data.
In shift registers, the flip flops are connected one after the other and all share the same clock. Each output of the flip flop is connected to the data input of the next flip flop in the chain. Such a circuit shifts the “bit array” stored in it by one position. Thereby, at each transition of the clock input there is shifting out of the last bit in the array and shifting in the data present at its input. Shift register may be multidimensional, which means that its stage output and data in may themselves be bit arrays. This particular type of shit register is implemented by running several shift registers of the same bit-length in parallel. Shift registers can have both serial and parallel output and input. They are known as: serial in, serial out (SISO), parallel in, serial out (PISO) or serial in, parallel out (SIPO). The last output and serial input can be connected to create a circular shift register. Bidirectional shift registers also exists ie L→R or R→L.
This type of shift registers, for each stage, will delay the input data by one clock cycle. Now we will take an example of 3 JK flip flops used as a serial-in/serial-out shift register.
Fig (1): Serial in/ Serial out shift register
Following output waveform will result from the above JK flip flop set up. See very clearly how by one clock cycle the data is shifted after each stage.
Fig (2): Serial in/ Serial out shift register output waveform.
This type of register also shifts data with each clock cycle just like Serial-in/Serial-out shift registers. The only difference is that internal stages are made available at the output, thus making the serial input data into parallel output data format. Now we will see an example of 4 D flip flops connected to create a serial-in/parallel-out shift register:
Fig (3): Serial in/ Parallel out shift register
The following output waveform is the waveform for the above shift register. Notice how the data is shifted after each stage by one clock cycle.
Here the data input is in parallel format from D1 to D4. To shift the data, the registers are clocked and the W/S control line is to be made “high”. To write the data to register, the W/S lone must be kept “low”. The system now acts as SISO (serial in serial out) shift register with D1 as the data input. However, as long as number of clock cycles is not more than the length of the data-string, the Data Output, Q, will be the parallel data read off in order.
Fig (4): Parallel in/ Serial out shift register circuit diagram.
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