Forums Engineering VHDL code for Half-Adder

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  • #16314

    kaushlendra
    Member

    Write VHDL code for Half-Adder

    #16315

    kaushlendra
    Member

    The code for Half_Adder is:-
    Library ieee;
    use ieee.std_logic_1164.all;
    entity Half-adder is
    port(a,b:in bit);
    port(sum,carry:out bit);
    end Half_adder
    begin
    sum<=a xor b;
    carry <= a and b;
    end data;

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